Patchwork [05,of,10] hgweb: move compline() closure out of compare()

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Submitter Yuya Nishihara
Date May 12, 2018, 3:35 a.m.
Message ID <4365cc3f60091ff071d1.1526096112@mimosa>
Download mbox | patch
Permalink /patch/31535/
State Accepted
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Yuya Nishihara - May 12, 2018, 3:35 a.m.
# HG changeset patch
# User Yuya Nishihara <yuya@tcha.org>
# Date 1522767248 -32400
#      Tue Apr 03 23:54:08 2018 +0900
# Node ID 4365cc3f60091ff071d19254e50e3074b64cb317
# Parent  1e645f7b2fd870569e56a0560a3c65c120319a8e
hgweb: move compline() closure out of compare()

Patch

diff --git a/mercurial/hgweb/webutil.py b/mercurial/hgweb/webutil.py
--- a/mercurial/hgweb/webutil.py
+++ b/mercurial/hgweb/webutil.py
@@ -575,50 +575,53 @@  def diffs(web, ctx, basectx, files, styl
             linerange, lineidprefix)
     return templateutil.mappinggenerator(_diffsgen, args=args, name='diffblock')
 
+def _compline(tmpl, type, leftlineno, leftline, rightlineno, rightline):
+    lineid = leftlineno and ("l%d" % leftlineno) or ''
+    lineid += rightlineno and ("r%d" % rightlineno) or ''
+    llno = '%d' % leftlineno if leftlineno else ''
+    rlno = '%d' % rightlineno if rightlineno else ''
+    return tmpl.generate('comparisonline', {
+        'type': type,
+        'lineid': lineid,
+        'leftlineno': leftlineno,
+        'leftlinenumber': "% 6s" % llno,
+        'leftline': leftline or '',
+        'rightlineno': rightlineno,
+        'rightlinenumber': "% 6s" % rlno,
+        'rightline': rightline or '',
+    })
+
 def compare(tmpl, context, leftlines, rightlines):
     '''Generator function that provides side-by-side comparison data.'''
 
-    def compline(type, leftlineno, leftline, rightlineno, rightline):
-        lineid = leftlineno and ("l%d" % leftlineno) or ''
-        lineid += rightlineno and ("r%d" % rightlineno) or ''
-        llno = '%d' % leftlineno if leftlineno else ''
-        rlno = '%d' % rightlineno if rightlineno else ''
-        return tmpl.generate('comparisonline', {
-            'type': type,
-            'lineid': lineid,
-            'leftlineno': leftlineno,
-            'leftlinenumber': "% 6s" % llno,
-            'leftline': leftline or '',
-            'rightlineno': rightlineno,
-            'rightlinenumber': "% 6s" % rlno,
-            'rightline': rightline or '',
-        })
-
     def getblock(opcodes):
         for type, llo, lhi, rlo, rhi in opcodes:
             len1 = lhi - llo
             len2 = rhi - rlo
             count = min(len1, len2)
             for i in xrange(count):
-                yield compline(type=type,
-                               leftlineno=llo + i + 1,
-                               leftline=leftlines[llo + i],
-                               rightlineno=rlo + i + 1,
-                               rightline=rightlines[rlo + i])
+                yield _compline(tmpl,
+                                type=type,
+                                leftlineno=llo + i + 1,
+                                leftline=leftlines[llo + i],
+                                rightlineno=rlo + i + 1,
+                                rightline=rightlines[rlo + i])
             if len1 > len2:
                 for i in xrange(llo + count, lhi):
-                    yield compline(type=type,
-                                   leftlineno=i + 1,
-                                   leftline=leftlines[i],
-                                   rightlineno=None,
-                                   rightline=None)
+                    yield _compline(tmpl,
+                                    type=type,
+                                    leftlineno=i + 1,
+                                    leftline=leftlines[i],
+                                    rightlineno=None,
+                                    rightline=None)
             elif len2 > len1:
                 for i in xrange(rlo + count, rhi):
-                    yield compline(type=type,
-                                   leftlineno=None,
-                                   leftline=None,
-                                   rightlineno=i + 1,
-                                   rightline=rightlines[i])
+                    yield _compline(tmpl,
+                                    type=type,
+                                    leftlineno=None,
+                                    leftline=None,
+                                    rightlineno=i + 1,
+                                    rightline=rightlines[i])
 
     s = difflib.SequenceMatcher(None, leftlines, rightlines)
     if context < 0: